It is clear that there are a number of areas today and in the future which applications will have increasingly large bandwidth data streams that will need to be collected and distributed in the most rapid and efficient way possible. Systems employing advanced slotted ring technology hold great potential for meeting a wide range of such needs.
A final implementation of the architecture would involve the development of a single chip node and a multi chip module ring. The technical risk could be reduced and an immediate operational capability provided by first implementing the node using VLSI chip technology and standard PCB packaging techniques.
The capabilities offered by the slotted ring are necessary for any application that requires large quantities of data resident in many and widespread data sources, and where there are many users of the totality of data. Key to the slotted ring architecture is the capability to select only the data required at any particular node, however the system can be configured to deny classified or sensitive data to particular nodes. In summary, the slotted ring architecture routes information from sources to destinations at hardware speeds with total discrimination capability.
II. Concept Description
The MADL Advanced Slotted Ring is a network technology which provides extremely high transfer rates between nodes and a unique capability to route information at these transfer speeds. The architecture consists of a number of nodes, each connected to two other nodes in such a manner as to form a ring. The ring can be arbitrarily scaled to any number of nodes as required. Each node receives information on one of these connections and transmits information on the other. Thus information is passed from node to node in a single direction around the ring.
The connections from node to node differ from those of all other ring networks in that they are made up of a comparatively large number of parallel conductors. This allows both the data transfer rate and the routing function to operate at a performance level orders of magnitude greater than that of the common serial ring network.
In the MADL slotted ring all nodes operate using the same clock signal. If there are N nodes in the ring, then each node is guaranteed 1/N of the clock pulses that it can use to transmit data. For example, if a 1 GHz clock is used in a ring with four nodes, then each node is guaranteed to be able to transmit data at a rate of 256 million messages per second. Each node places data on the ring simultaneously; the remaining N-1 clock pulses are used to transfer messages from node to node around the ring.
Messages sent on the ring consist, in part, of data and a corresponding pattern field. Each bit in the message is transferred from node to node over one of the parallel conductors mentioned above. Expanding on the example above, if the data part of the messages were 256 bits in width (32 bytes) then there would be 256 conductors between each and every node dedicated to carrying the data transferred on the ring. The data transmit rate from each node would be 64 gigabits per second (8 gigabytes per second). The node to node transfer rate would be 256 gigabits/second (32 gigabytes per second) and the total transfer capacity of this four node ring would be one terabit per second (128 gigabytes per second).
The pattern field mentioned above, identifies the data type contained in each message. A pattern, for example, may correspond to the velocity vector for the inertial navigation system on an F/A-18 or the instantaneous load factor from a Boeing 777 airliner as computed by a workstation. The ring uses the pattern field to partition data as it is distributed. Each node can be dynamically configured to extract any combination of data types present on the ring consistent with the security mechanisms described below. The matching function required to accomplish this is performed in hardware at ring clock speeds.
Each node can be dynamically reconfigured to selectively extract only the data that it requires to perform its function. This reconfiguration is accomplished by altering the contents of memory locations that make up part of the pattern matching circuitry at each node. There is a memory location that corresponds to each pattern in the set of all possible patterns. By hardwiring some of these memory locations to disable reception, it is possible to deny access to an arbitrary set of patterns at any given node. Therefore the set of patterns a given node receives can be changed dynamically via software, statically via hardware (for multi-level security applications), or a combination of the two methods. This capability to rapidly extract from large volumes of data, only the data needed by node applications, results in a significant reduction in the bandwidth requirement for the link connecting each of the ring nodes to data processors. It also greatly reduces the amount of processing required at the workstations or other processing elements connected to each node.
In order to attain the performance levels in the terabit regime the physical size of the ring network must be constrained. This suggests the use of multi-chip module technology combined with a full custom VLSI implementation of each node, or possibly multiple nodes on a single chip.
A parallel ring will demand a large number of output drivers (and inputs as well) to be fabricated on each chip. Since these drivers occupy a comparatively large area and consume a corresponding quantity of power, their use comes at a premium. This fact, combined with the architectures innate capability of reducing the total quantity of data to only that needed at each node, argues for a serial interface from each node to external devices. This conserves input/output real estate on each chip for the important function of ring performance albeit at the cost of additional circuit complexity needed to implement the serial interface.
Another advantage of implementing a serial interface from ring nodes to external devices is that industry standard communication protocols can be leveraged to provide process to process communication without the need to develop special purpose operating system drivers for the purpose. If the performance requirements for the serial link are met by a current or developing industry standard (e.g.: ATM, gigabit Ethernet, Firewire) then connection to a large number of commercially available processing platforms becomes an easy task. This will have the desired result of broadening the applications base of the underlying Advanced Slotted Ring Technology. A third advantage of the serial interface is that it enables the connection of multiple geographically distance slotted rings in applications that involve data transfer intensive loci.
Using the ring topology allows a higher speed of operation relative to competing topologies for the following reasons. First, the decision of where to route an incoming message is very simple: it is either passed on to the next node in the ring, or it isn’t. Simple decisions like this can be made very quickly in hardware. Secondly, the outputs of each node on the ring need only drive a single set of inputs, namely inputs of the next node. This allows a large number of nodes to be connected without the need to compromise speed with output drive capability incurred when driving multiple inputs (as in the case for a bus).
The ring is synchronous, meaning that a single clock pulse is used to operate all nodes on the ring. One advantage of a synchronous transfer is the predictability of the data transfer timing. Also, it is typically easier to design a synchronous network than to design an asynchronous one. The simplicity of a design generally translates to less hardware, less power, greater density and therefore greater speed.
The advanced slotted ring technology concept provides for fair (no nodes are "bandwidth starved"), deterministic and easily predictable access to the communication media by each node. Additionally, there is no contention overhead involved in resolving which node has access to the ring at any given time. Each node is allocated an equal proportion of the total bandwidth. In all other network topologies except point-to-point, one processor may have to wait for a connection to be freed by another processor before it can transmit its data. For example, consider the crossbar switch. Suppose that two processors both want to send data to a third processor. Since there is only one path to the receiving processor, one of the two transmitting processors must wait until the other processor is finished before transmitting its data. Since processors may not know when the other processors want to transmit, it is very difficult to predict when contention will occur. The slotted ring eliminates this problem by providing a guaranteed communications slot for each processor. Processors can plan their communications activities around this guaranteed slot, knowing that it will always be available to them. This is particularly important in applications that require on-time delivery of data.
III. Technical Objectives
The challenges in implementing the advanced slotted ring architecture as presented in section II above are twofold. The first major challenge involves the implementation of the data transfer functions ring on a single chip. Because the architecture demands very wide data paths, getting these on and off the chip will not be trivial. High speed output drivers consume a relatively large amount of power and chip real estate. Implementing an industry standard high performance serial interface on the same die will further tax the current state of the art in VLSI technology.
The second major challenge involves the packaging of the nodes into a ring. In order to fully exploit the performance gained from implementing the nodes in chip form, the ring physical dimensions must be minimized. A ring topology is advantageous in that it is easy to layout an arbitrarily large number of nodes and still keep the node to node distance constant. However this node to node distance must be minimized in order to maximize ring performance. This fact argues for the implementation of a ring network on a multi-chip module. There remain topological issues to be solved such as routing the serial connections to external devices that are located outside the multi-chip module.
The above challenges present a reasonable level of technical risk if a non-trivial level of performance is desired. One element of this risk involves the density required to implement both a wide ring and an industry standard serial interface on a single die. The current limited or non-existent availability of a standard serial interface design that can be integrated on-chip with the ring functions is an important aspect of this challenge. This problem can be addressed early in the development cycle by implementing a node as a two chip set. One chip would provide the advanced slotted ring functionality and implement an interface to the second chip. The second chip would provide access to external devices over a serial industry standard interface. This chip would be procured off-the-shelf, thus avoiding the issue of design availability.
A survey of VLSI chip technology indicates that ring data widths of 256 bits (32 bytes) and a ring shift clock frequency of 200 megahertz are currently attainable. This would yield node to node data transfer rate of 51.2 gigabits per second (6.4 gigabytes per second) on a ring implemented with VLSI and printed circuit board technology. Additionally, this technology supports enough on chip memory to support 256 thousand different types of data.
IV. Benefits and Potential Applications of the Advanced Slotted Ring Technology
Whereas there are many potential applications of the slotted ring including uses in the areas of biomedicine, transportation, and information processing, we will focus on the following examples to present a better understanding of the capabilities offered through the use of this advanced technology.
- Advanced Military Communications
In the area of advanced military communications systems, the Advanced Slotted Ring can be instrumental in the intelligent distribution and processing of the very large quantity of raw information produced by these systems. On example of one of these systems is the ACN being developed by the Sensor Technology Office at the Defense Advanced Research Projects Administration. This system will be capable of receiving and re-transmitting military communications over the complete band from 20 to 2800 Megahertz. Many different signal formats are accommodated including SINGARS, HAVE QUICK, EPLRS, JTIDS, and cellular phone. The demodulation of these various signals produces many separate high bit rate data streams. The Advanced Slotted Ring can make possible applications requiring portions of these disparate data streams to be combined in order to obtain a synthesized result. A schematic portraying the employment of ASRT in the ACN system is shown in below.
Advanced Slotted Ring employed in ACN system
- Distributed Shared Memory
For modern high speed computers operating in parallel the use of distributed shared memory (DSM) with high data rate communication is a necessity. One commonly used metric for the effectiveness of the communication mechanism used in DSM systems is the ratio (called the Q ratio) of the time required to compute a result to the time required to transfer it to a process running on a remote processor. The best reported Q ratios have typically been around 100 for very specialized and costly systems. Because the advanced slotted ring architecture provides deterministic low latency bandwidth at very high performance levels it has the potential to attain Q ratios approaching one. This is an essential ingredient in providing distributed shared memory capabilities to modern computing systems.
- Video Applications
Where there is a need to distinguish specific characteristics from a large number of real time video frames the slotted ring is ideal for rapid discrimination and simultaneous distribution of the large number of pixels involved to many processors. The traditional image processing task where a number of algorithms are being applied to a single scene is one commonly used in the intelligence and biomedical fields.
- Flight Safety and Maintenance Diagnostics
MADL demonstrated in the TTMA program that flight operations could be significantly improved by recording and making use of the large amount of data passing over an aircraft digital data bus. The digital data generated during a flight includes essentially all aspects of the aircraft flight as well as the health of the electromechanical sub-systems on board. By rapidly processing this data, it becomes possible to derive, in a timely manner, mission-critical information such as aircraft flight profile, enemy radar locations, weapon release events, electronic warfare threats and bomb damage assessment for military aircraft and flight safety information such as engine performance on civil or military aircraft. Executing the processing in a timely manner requires a system which accepts multiple high speed data streams and rapidly extracts the data required by each user. This can also be applied to data transmitted via telemetry in real time. The demonstration of the TTMA proof of concept established that the slotted ring’s unique capabilities resulted in the timely transition from recorded or real time data to information necessary for making critical decisions by the appropriate authorities.
